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| intel ? 80321 i/o processor datasheet product features core features ? integrated intel ? xscale ? core ? arm* v5t instruction set ? arm v5e dsp extensions ? 400 mhz and 600 mhz ? write buffer, write-back cache pci bus interface ? pci local bus specification , rev. 2.2 compliant ? pci-x addendum to the pci local bus specification , rev. 1.0a ? 64-bit/66 mhz operation in pci mode ? 64-bit/133 mhz operation in pci-x mode ? support 32-bit pci initiators and targets ? four split read requests as initiator ? eight split read requests as target ? 64-bit addressing support memory controller ? pc200 double data rate (ddr) sdram ? up to 1 gbyte of 64-bit ddr sdram ? up to 512 mbytes of 32-bit ddr sdram ? single-bit error correction, multi-bit support (ecc) ? 1024-byte posted memory write queue ? 40- and 72-bit wide memory interface address translation unit ? 2 kbyte or 4 kbyte outbound read queue ? 4 kbyte outbound write queue ? 4 kbyte inbound read and write queue ? connects internal bus to pci/pci-x bus dma controller ? two independent channels connected to internal bus ? up to 1064 mbytes/s burst support in pci-x mode ? up to 1600 mbytes/s burst support for internal bus ? two 1-kbyte queues in ch-0 and ch-1 ?2 32 addressing range on internal bus interface ?2 64 addressing range on pci interface application accelerator unit ? performs xor on read data ? compute parity across local memory blocks ? 1 kbyte/512-byte store queue i 2 c bus interface units ?two separate i 2 c units ? serial bus ? master/slave capabilities ? system management functions ssp serial port ? full-duplex synchronous serial interface ? supports 7.2 khz to 1.84 mhz bit rates peripheral performance monitoring unit ? one dedicated global time stamp counter ? fourteen programmable event counters ? three control/status registers timers ? two dual-programmable 32-bit timers ? watchdog timer 544-ball, plastic ball grid array (pbga) eight general purpose i/o pins document number: 273518-004 february 2003
intel ? 80321 i/o processor 2 february 2003 datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel? intel? 80321 i/o processor may contain design defects or errors known as errata which may cause the product to devia te from published specifications. current characterized errata are available on request. intel ? internal code names are subject to change. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright? intel corporation, 2003 alertview, i960, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, commerce cart, ct connect, ct media, dialogic, dm3, etherexpress, etox, flashfile, gatherround, i386, i486, icat, icomp, insight960, instantip, intel, intel logo, intel386, i ntel486, intel740, inteldx2, inteldx4, intelsx2, intel chatpad, intel create&share, intel dot.station, intel gigablade, intel inbusiness, intel in side, intel inside logo, intel netburst, intel netstructure, intel play, intel play logo, intel pocket concert, intel singledriver, intel speedstep, intel str ataflash, intel teamstation, intel weboutfitter, intel xeon, intel xscale, itanium, jobanalyst, landesk, lanrover, mcs, mmx, mmx logo, netport, netportexpre ss, optimizer logo, overdrive, paragon, pc dads, pc parents, pentium, pentium ii xeon, pentium iii xeon, performance at your command, proshar e, remoteexpress, screamline, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside, the journey inside, this way in, tokenexpress, trillium, vivonic, and vtune are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. intel ? 80321 i/o processor datasheet february 2003 3 contents 1.0 introduction................................................................................................................ .........7 1.1 about this document............................................................................................7 1.1.1 terminology..............................................................................................7 1.1.2 other relevant documents ......................................................................8 1.2 about the intel ? 80321 i/o processor ...................................................................9 2.0 features .................................................................................................................... .......11 2.1 internal bus .........................................................................................................11 2.2 dma controller....................................................................................................11 2.3 address translation unit .....................................................................................12 2.4 messaging unit....................................................................................................12 2.5 memory controller...............................................................................................12 2.6 peripheral bus interface...................................................................................... 12 2.7 application accelerator unit ................................................................................13 2.8 performance monitoring unit...............................................................................13 2.9 i 2 c bus interface units........................................................................................13 2.10 synchronous serial port unit ..............................................................................13 3.0 package information ........................................................................................................1 4 3.1 package introduction........................................................................................... 14 3.1.1 functional signal definitions ..................................................................14 3.1.2 544-lead pbga package ...................................................................... 25 3.2 package thermal specifications .........................................................................39 3.2.1 thermal specifications ...........................................................................39 3.2.1.1 ambient temperature................................................................39 3.2.1.2 case temperature ....................................................................39 3.2.1.3 thermal resistance ..................................................................39 3.2.2 thermal analysis....................................................................................40 3.3 socket information ..............................................................................................41 3.3.1 socket-header vendor...........................................................................41 3.3.2 burn-in socket vendor ........................................................................... 41 3.3.3 shipping tray vendor.............................................................................41 3.3.4 logic analyzer interposer vendor .......................................................... 41 3.3.5 jtag emulator vendor .......................................................................... 42 4.0 electrical specifications................................................................................................... .43 4.1 absolute maximum ratings.................................................................................43 4.2 v ccpll pin requirements ................................................................................... 43 4.3 targeted dc specifications.................................................................................44 4.4 targeted ac specifications.................................................................................46 4.4.1 clock signal timings ..............................................................................46 4.4.2 pci interface signal timings ..................................................................47 4.4.3 ddr sdram interface signal timings .................................................. 48 4.4.4 peripheral bus interface signal timings ................................................ 48 4.4.5 i 2 c interface signal timings...................................................................49 4.4.6 ssp interface signal timings................................................................. 49 4.4.7 boundary scan test signal timings ...................................................... 50 4.5 ac timing waveforms ........................................................................................51 4.6 ac test conditions ............................................................................................. 55 intel ? 80321 i/o processor 4 february 2003 datasheet figures 1 intel ? 80321 i/o processor functional block diagram ....................................... 10 2 544-lead pbga package (top view)................................................................. 25 3 544-lead pbga package (bottom view) ........................................................... 26 4 ball map - left side - top view...........................................................................27 5 ball map - right side - top view ........................................................................ 28 6 thermocouple attachment - no heatsink ........................................................... 39 7v ccpll lowpass filter ........................................................................................ 43 8 clock timing measurement waveforms ............................................................. 51 9 output timing measurement waveforms ........................................................... 51 10 input timing measurement waveforms .............................................................. 52 11 i 2 c interface signal timings................................................................................ 52 12 ddr sdram write timings ............................................................................... 53 13 ddr sdram read timings ............................................................................... 54 14 ac test load for all signals except pci and ddr sdram ............................... 55 15 pci/pci-x tov(max) rising edge ac test load............................................... 55 16 pci/pci-x tov(max) falling edge ac test load .............................................. 55 17 pci/pci-x tov(min) ac test load ....................................................................56 18 pci_rst# vs. pwrdelay timings during power-up ...................................... 56 19 pci_rst# vs. pwrdelay timings during power-down ................................. 56 intel ? 80321 i/o processor datasheet february 2003 5 tables 1 related documentation.........................................................................................8 2 pin description nomenclature.............................................................................14 3 ddr sdram signals ..........................................................................................15 4 peripheral bus interface signals .........................................................................16 5 pci bus signals ..................................................................................................19 6 serial port interface signals................................................................................ 20 7 miscellaneous signals.........................................................................................21 8 pin mode behavior ..............................................................................................23 9 544-lead pbga package - alphabetical ball listing .......................................... 29 10 544-lead pbga package - alphabetical signal listing ...................................... 34 11 544-lead pbga package thermal characteristics ............................................ 40 12 socket-header vendor........................................................................................41 13 burn-in socket vendor ........................................................................................ 41 14 shipping tray vendor..........................................................................................41 15 logic analyzer interposer vendor .......................................................................41 16 jtag emulator vendor ....................................................................................... 42 17 operating conditions...........................................................................................43 18 dc characteristics ..............................................................................................44 19 i cc characteristics ..............................................................................................45 20 clock timings......................................................................................................46 21 pci signal timings.............................................................................................. 47 22 ddr sdram signal timings ..............................................................................48 23 peripheral bus signal timings ............................................................................ 48 24 i 2 c signal timings............................................................................................... 49 25 ssp signal timings............................................................................................. 49 26 boundary scan test signal timings ................................................................... 50 27 dat mode timings.............................................................................................. 50 28 bypass mode timings ......................................................................................... 50 29 ac measurement conditions ..............................................................................55 intel ? 80321 i/o processor 6 february 2003 datasheet revision history date revision # description january 2003 004 in table 7 ?miscellaneous signals? : for signal gpio[4]/sda1, added sentence ?2.7k pull-up is required.? for signal gpio[5]/scl1, added sentence ?2.7k pull-up is required.? for signal gpio[6]/sda0, added sentence ?2.7k pull-up is required.? for signal gpio[7]/scl0, added sentence ?2.7k pull-up is required.? added signal p_bmi with count and type values, and description. in table 8 ?pin mode behavior? : changed rdyrcv# signal from vi to vo for reset. added signal p_bmi with reset and norm values. in table 9 ?544-lead pbga package - alphabetical ball listing? : changed ae23 from nc2 to p_bmi. in table 10 ?544-lead pbga package - alphabetical signal listing? : changed nc2 to p_bmi. in section 4.3, ?targeted dc specifications? : revised notice to state ?the spec- ifications are subject to change without notice. contact your local intel repre- sentative before finalizing a design.? revised table 19 ?i cc characteristics? . in table 22 ?ddr sdram signal timings? : added tva6 with description, and minimum signal timing value. in figure 13 ?ddr sdram read timings? : revised signal timing relationships for tva5 and tva6 to ck and rcveno#. added tva6 signal timing relationship to reveni# and dqs. added figure 18 ?pci_rst# vs. pwrdelay timings during power-up? . added figure 19 ?pci_rst# vs. pwrdelay timings during power-down? . june 2002 003 formatting changes. june 2002 002 removed advance information designation. february 2002 001 initial release. datasheet february 2003 7 1.0 introduction 1.1 about this document this is the intel ? 80321 i/o processor datasheet . this datasheet contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. detailed functional descriptions other than parametric performance is published in the intel ? 80321 i/o processor developer?s manual . intel corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. intel retains the right to make changes to these specifications at any time, without notice. in particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. in fact, this document does not imply a commitment by intel to design, manufacture, or sell the product described herein. 1.1.1 terminology to aid the discussion of the intel ? 80321 i/o processor (80321) architecture, the following terminology is used: downstream at or toward a pci bus with a higher number (after configuration) host processor processor located upstream from the 80321 local processor intel ? xscale ? core (arm* architecture compliant) within the 80321 local bus 80321 internal bus local memory memory subsystem on the intel ? xscale ? core pc200 ddr sdram or peripheral bus interface busses upstream at or toward a pci bus with a lower number (after configuration) intel ? 80321 i/o processor introduction 8 february 2003 datasheet 1.1.2 other relevant documents table 1. related documentation document title document# / contact intel ? 80312 i/o companion chip developer?s manual 273410 intel ? 80312 i/o companion chip specification update 273416 intel ? 80200 processor based on intel ? xscale ? microarchitecture developer?s manual 273411 intel ? 80310 i/o processor chipset with intel ? xscale ? microarchitecture design guide 273354 intel ? 80200 processor based on intel ? xscale ? microarchitecture datasheet 273414 intel ? 80200 processor based on intel ? xscale ? microarchitecture specification update 273415 pci local bus specification, revision 2.2 pci special interest group 1-800-433-5177 http://www.pcisig.com/home pci-x addendum to the pci local bus specification, revision 1.0a pci-to-pci bridge architecture specification, revision 1.1 pci system design guide , revision 1.0 pci hot-plug specification, revision 1.0 pci bus power management interface specification , revision 1.1 i 2 c peripherals for microcontrollers philips semiconductor* advanced configuration and power interface specification, revision 1.0 (acpi) http://www.teleport.com/~acpi/ note: also see our product website at: http://developer.intel.com/design/iio/ . intel ? 80321 i/o processor introduction datasheet february 2003 9 1.2 about the intel ? 80321 i/o processor the 80321 is a single-function device that integrates the intel ? xscale ? core with intelligent peripherals, including a pci bus application bridge. the 80321 consolidates into a single system: intel ? xscale ? core pci - local memory bus address translation unit messaging unit direct memory access (dma) controller peripheral bus interface unit integrated memory controller performance monitor application accelerator tw o i 2 c bus interface units synchronous serial port unit eight general purpose input output (gpio) ports it is an integrated processor that addresses the needs of intelligent i/o applications and helps reduce intelligent i/o system costs. the pci bus is an industry standard, high performance, low latency system bus. the 80321 pci bus is capable of 133 mhz operation in pci-x mode as defined by the pci-x addendum to the pci local bus specification, revision 1.0a. also, the processor supports a 66 mhz conventional pci mode as defined by the pci local bus specification, revision 2.2. the addition of the intel ? xscale ? core brings intelligence to the pci bus application bridge. the 80321 is a single-function pci device. this function represents the address translation unit. the address translation unit is an ?application bridge? as defined by the pci-x addendum to the pci local bus specification, revision 1.0a. the 80321 contains pci configuration space accessible through the pci bus. intel ? 80321 i/o processor introduction 10 february 2003 datasheet figure 1 is a block diagram of the 80321. figure 1. intel ? 80321 i/o processor functional block diagram a7610-02 64-bit / 32-bit pci bus ddr i/f unit i 2 c serial bus serial bus i 2 c bus interface application accelerator performance monitoring unit ssp serial bus address translation unit intel ? 80321 i/o processor two dma channels intel ? xscale ? core internal bus pbi unit (flash) 32-bit i/f 72-bit i/f messaging unit notes: intel xscale microarchitecture is arm* architecture compliant. * other brands and names are the property of their respective owners. intel ? 80321 i/o processor features datasheet february 2003 11 2.0 features the 80321 combines the intel ? xscale ? core with powerful new features to create an intelligent i/o processor. this single-function pci device is fully compliant with the pci local bus specification, revision 2.2. 80321-specific features include: the subsections that follow briefly overview each feature. refer to the appropriate chapter in the intel ? 80321 i/o processor developer?s manual for full technical descriptions. the 80321 core is based upon the intel ? xscale ? core. the core processor operates at a maximum frequency of 600 mhz. the instruction cache is 32 kbytes in size and is 32-way set associative. also, the core processor includes a data cache that is 32 kbytes and is 32-way set associative and a mini data cache that is 2 kbytes and is 2-way set associative. the 80321 includes 8 general purpose i/o (gpio) pins. 2.1 internal bus the internal bus is a high-speed interconnect between all internal units and controllers. the internal bus operates at 200 mhz and is 64 bits wide. 2.2 dma controller the dma controller allows low-latency, high-throughput data transfers between pci bus agents and the local memory. two separate dma channels accommodate data transfers on the pci bus. the dma controller supports chaining and unaligned data transfers. it is programmable through the intel ? xscale ? core only. address translation unit dma controller memory controller performance monitoring unit peripheral bus interface synchronous serial port unit application accelerator unit messaging unit i 2 c bus interface units i 2 o* compatibility intel ? 80321 i/o processor features 12 february 2003 datasheet 2.3 address translation unit the address translation unit (atu) allows pci transactions direct access to the 80321 local memory. the atu supports transactions between pci address space and the 80321 address space. address translation is controlled through programmable registers accessible from both the pci interface and the intel ? xscale ? core. dual access to registers allows flexibility in mapping the two address spaces. the atu also supports the following extended capability configuration headers: 1. power management header as defined by pci bus power management interface specification , revision 1.1. 2. message signaled interrupt capability structure specified in pci local bus specification, revision 2.2. 3. pci-x capabilities list item specified in the pci-x addendum to the pci local bus specification, revision 1.0a. 2.4 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 80321. it uses interrupts to notify each system when new data arrives. the mu has four messaging mechanisms: message registers doorbell registers circular queues index registers each allows a host processor or external pci device and the 80321 to communicate through message passing and interrupt generation. 2.5 memory controller the memory controller allows direct control of a pc200 ddr sdram memory subsystem. it features programmable chip selects and support for error correction codes (ecc). external memory may be configured as pci addressable memory or private 80321 memory. 2.6 peripheral bus interface the peripheral bus interface unit (pbi) is a data communication path to certain components of a 80321 hardware system that do not have pci bus interfaces and/or do not optimally reside on the pci bus. examples of such components include flash memory and dsp host interface ports. the pbi allows the processor to manipulate data and interact with these components in the i/o environment. to perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 32-bit data transfers. the bus has a 33 mhz, 66 mhz and a 100 mhz operating mode. intel ? 80321 i/o processor features datasheet february 2003 13 2.7 application accelerator unit the application accelerator unit transfers blocks of data to and from the local memory and performs boolean operations, such as xor, on the data. 2.8 performance monitoring unit the performance monitoring unit (pmon) allows various events on the 80321 to be monitored. the 14 event counters may be programmed to observe events selected from a pre-defined set of events. 2.9 i 2 c bus interface units there are two i 2 c (inter-integrated circuit) bus interface units that allow the intel ? xscale ? core to serve as a master and slave device residing on the i 2 c bus. the i 2 c unit uses a serial bus developed by philips semiconductor* consisting of a two-pin interface. the bus allows the 80321 to interface to other i 2 c peripherals and microcontrollers for system management functions. it requires a minimum of hardware for an economical system to relay status and reliability information on the i/o subsystem to an external device. also refer to i 2 c peripherals for microcontrollers (philips semiconductor*). 2.10 synchronous serial port unit the synchronous serial port (ssp) unit is a full-duplex synchronous serial interface. it may connect to a variety of external analog-to-digital (a/d) converters, audio and telecom codecs, and many other devices which use serial protocols for transferring data. it supports the national microwire*, texas instrument* synchronous serial protocol, and the motorola* serial peripheral interface (spi) protocol. intel ? 80321 i/o processor package information 14 february 2003 datasheet 3.0 package information 3.1 package introduction the 80321 is offered in a plastic ball grid array (pbga) package. this is a perimeter array package with 508 ball connections in the outer area of the package and a square 6x6 grid of rows of ball connections in the middle area of the package. see figure 3 ?544-lead pbga package (bottom view)? on page 26 . 3.1.1 functional signal definitions this section defines the pins and signals. table 2. pin description nomenclature symbol description i input pin only o output pin only i/o pin may be either an input or output. od open drain pin - pin must be connected as described. sync(...) synchronous. signal meets timings relative to an input clock. sync(p) synchronous to p_clk sync(m) synchronous to m_ck[2:0] sync(pb) synchronous to pb_clk sync(ss) synchronous to sscko sync(t) synchronous to tck async asynchronous. inputs may be asynchronous relative to all clocks. all asynchronous signals are level-sensitive. rst(p) the pin is reset with p_rst# . rst(m) the pin is reset with m_rst# . note that m_rst# is asserted when p_rst# is asserted or pcsr[5] is set with software. rst(t) the pin is reset with trst# . (configuration pin) these pins are used during reset to configure the processor. these pins have internal pullup resisters which are turned on when p_rst# is low. to configure the pin low connect a 4.7k ? resister from the pin to ground. by default the pin is configured high. intel ? 80321 i/o processor package information datasheet february 2003 15 table 3. ddr sdram signals name count type description rcveni# 1i receive enable in provides delay information for enabling the input receivers and must be connected to rcveno# of the 80321. rcveno# 1o receive enable out must be connected to rcveni# of the 80321 and be trace length matched to clock trace plus average dq traces. m_ck[2:0] 3o memory clocks are used to provide the positive differential clocks to the external sdram memory subsystem. m_ck[2:0]# 3o memory clocks are used to provide the negative differential clocks to the external sdram memory subsystem. m_rst# 1o async memory reset indicates when the memory subsystem has been reset with p_rst# or a software reset. sa[12:0] 13 o sync(m) rst(m) memory address bus carries the multiplexed row and column addresses to the sdram memory banks. for sa[10] , see note 1 . sba[1:0] 2o sync(m) rst(m) sdram bank address indicates which of the sdram internal banks are read or written during the current transaction. see note 1 . sras# 1o sync(m) rst(m) sdram row address strobe indicates the presence of a valid row address on the multiplexed address bus sa[12:0] . see note 1 . scas# 1o sync(m) rst(m) sdram column address strobe indicates the presence of a valid column address on the multiplexed address bus sa[12:0] . see note 1 . swe# 1o sync(m) rst(m) sdram write enable indicates that the current memory transaction is a write operation. see note 1 . sce[1:0]# 2o sync(m) rst(m) sdram chip select enables the sdram devices for a memory access (physical banks 0 and 1). see note 1 . scke[1:0] 2o sync(m) rst(m) sdram clock enable enables the clocks for the sdram memory. deasserting places the sdram in self-refresh mode. see note 1 . dq[63:0] 64 i/o sync(m) rst(m) sdram data bus carries 64-bit data to and from memory. during a data cycle, read or write data is present on one or more contiguous bytes. during write operations, unused pins are driven to determinate values. see note 1 . scb[7:0] 8i/o sync(m) rst(m) sdram ecc check bits carry the 8-bit ecc code to and from memory during data cycles. see note 1 . dqs[8:0] 9i/o sync(m) rst(m) sdram data strobes carry the strobe signals which are used to capture data on the data bus. see note 1 . sdqm[8:0] 9o sync(m) rst(m) sdram data mask controls which bytes on the data bus should be written. when sdqm[8:0] is asserted, the sdram devices do not accept valid data from the byte lanes. see note 1 . v ref 1i sdram voltage reference is used to supply the reference voltage to the differential inputs of the memory controller pins. note: 1. these pins remain functional for 20 m_ck[2:0] periods after m_rst# is asserted for a warm boot. the designated rst(m) state applies after 20 m_ck[2:0] periods after m_rst# is asserted. for more details, refer to the mcu chapter of the intel ? 80321 i/o processor developer?s manual . intel ? 80321 i/o processor package information 16 february 2003 datasheet table 4. peripheral bus interface signals (sheet 1 of 3) name count type description ad[31:0] 32 i/o sync(pb) rst(m) address / data bus during an address cycle bits 31-2 contain the physical word address and bits 1-0 specify the number of data transfers during the bus transaction. 00= 1 transfer 01= 2 transfers 10= 3 transfers 11= 4 transfers. during a data cycle bits 31-0, 15-0 or 7-0 contain valid data, depending on the corresponding 32-, 16- or 8-bit bus width. during 16- and 8-bit bus write operations the unused bus pins are driven to determinate values. a[3:2] 2o sync(pb) rst(m) address [3:2] carries a demultiplexed version of bits 3 and 2 of the address bus. during an address cycle a[3:2] matches ad[3:2] . during a bursted read or write data cycle a[3:2] represents the current dword address in the bursted transaction. be[3:0]# 4o sync(pb) rst(m) byte enables select which of up to four data bytes on the bus participate in the current bus access. the byte enables are asserted during the address cycle. these signals do not toggle during a burst and they remain active through the last data cycle. byte enable encoding is dependent on the bus width: 32-bit bus: be[3]# enables data on ad[31:24] be[2]# enables data on ad[23:16] be[1]# enables data on ad[15:8] be[0]# enables data on ad[7:0] 16-bit bus: be[3]# enables data on ad[15:8] be[2]# is not used (state is high) be[1]# becomes address bit 1 ( a[1] ) be[0]# enables data on ad[7:0] 8-bit bus: be[3]# is not used (state is high) be[2]# is not used (state is high) be[1]# becomes address bit 1 ( a[1] ) be[0]# becomes address bit 0 ( a[0] ) for 16- and 8-bit bus accesses these address bits are asserted in conjunction with a[3:2] . ale 1o sync(pb) rst(m) address latch enable indicates the transfer of a physical address. the pin is asserted during the first address cycle and deasserted during the second address cycle. the pin floats whenever the bus is relinquished to an external device ads# 1o sync(pb) rst(m) address strobe indicates a valid address and the start of a new bus access. the pin is asserted during the second address cycle and deasserted during the first data cycle. the pin floats whenever the bus is relinquished to an external device pb_clk 1o peripheral bus clock is the reference clock for all signals on the peripheral bus. w/r# 1o sync(pb) rst(m) write / read indicates whether the bus access is a write or a read with respect to the 80321 and is valid during the entire bus access. this pin may be used to control the oe# input on the flash rom. the pin floats whenever the bus is relinquished to an external device 0 = read 1 = write intel ? 80321 i/o processor package information datasheet february 2003 17 fwe# 1o sync(pb) rst(m) flash write enable indicates whether the bus access is a write or a read with respect to the 80321 and is valid during the entire bus access. this pin is used for flash memory accesses and controls the swe# input on the rom. the pin floats whenever the bus is relinquished to an external device. 0 = write 1 = read den# 1o sync(pb) rst(m) data enable indicates data transfer cycles during a bus access. den# is asserted at the start of the first data cycle and deasserted at the end of the last data cycle. the pin is used to provide control for data transceivers connected to the bus. the pin floats whenever the bus is relinquished to an external device blast# 1o sync(pb) rst(m) burst last indicates the last data transfer of a bus access. blast# remains active when wait states are inserted and becomes inactive after the final data transfer is complete. the pin floats whenever the bus is relinquished to an external device rdyrcv# 1i/o sync(pb) rst(m) ready / recover during a data cycle the pin indicates that data may be sampled or removed. 0 = sample data 1 = insert wait state during a recover state the pin indicates that the recover state is repeated. this function allows slow external devices longer to float their pins before the next address is driven. 0 = insert recovery state 1 = recovery complete note : pbi base address register 0 bit 9 (flash window enable) is enabled for flash by default to support the boot process. see pbbar0 description in the 80321 i/o processor developer ? s manual. hold 1i sync(pb) hold is used by an external device to request access to the bus. holda 1o sync(pb) rst(m) hold acknowledge indicates to an external device that it has been granted access to the bus. pb_rst# 1o async peripheral bus reset indicates when the peripheral bus has been reset with p_rst# or a software reset. pce[5]# / pbi100mhz# (configuration pin) 1i/o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. peripheral bus 100 mhz enable is latched at the deasserting edge of p_rst# and it indicates the speed at which the pbi bus operates. [ pbi100mhz# , pbi66mhz# ] 11 = 33 mhz (default mode) 10 = 66 mhz 01 = 100 mhz 00 = undefined (reserved - do not use) pce[4]# / pbi66mhz# (configuration pin) 1i/o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. peripheral bus 66mhz enable is latched at the deasserting edge of p_rst# and it indicates the speed at which the pbi bus operates. [ pbi100mhz# , pbi66mhz# ] 11 = 33 mhz (default mode) 10 = 66 mhz 01 = 100 mhz 00 = undefined (reserved - do not use) table 4. peripheral bus interface signals (sheet 2 of 3) name count type description intel ? 80321 i/o processor package information 18 february 2003 datasheet pce[3]# / p_boot16# (configuration pin) 1o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. peripheral bus boot width 16 enable specifies the width of the peripheral bus for flash accesses during boot up. 0 = 16-bit bus width (requires pull-down resistor) 1 = 8-bit bus width (default mode) pce[2]# / 32bitpci# (configuration pin) 1 i/o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. 32 bit pci is latched at the deasserting edge of p_rst# and it indicates the width of the pci-x bus to the pci-x status register (bit 16 of the pci-x status register). 0 = 32-bit pci-x bus (requires pull-down resistor) 1 = 64-bit pci-x bus (default mode) pce[1]# / retry (configuration pin) 1 i/o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. retry is latched at the deasserting edge of p_rst# and it determines when the primary pci interface disables pci configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the pci configuration and status register. 0 = configuration cycles enabled (requires pull-down resistor) 1 = retry enabled (default mode) pce[0]# / rst_mode# (configuration pin) 1 i/o sync(pb) rst(m) peripheral chip enables specify which of the six memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. reset mode is latched at the deasserting edge of p_rst# and it determines when the 80321 is held in reset until the intel ? xscale ? microprocessor reset bit is cleared in the pci configuration and status register. 0 = hold in reset (requires pull-down resistor) 1 = don ? t hold in reset (default mode) width[1:0] 2o sync(pb) rst(m) width denotes the physical memory attributes for a bus transaction. the pins float whenever the bus is relinquished to an external device. 00 = 8 bits wide 01 = 16 bits wide 10 = 32 bits wide 11 = reserved table 4. peripheral bus interface signals (sheet 3 of 3) name count type description intel ? 80321 i/o processor package information datasheet february 2003 19 table 5. pci bus signals (sheet 1 of 2) name count type description p_ad[31:0] 32 i/o sync(p) rst(p) pci address/data is the multiplexed pci address and bottom 32 bits of the data bus. p_ad[63:32] 32 i/o sync(p) rst(p) pci data is the upper 32 bits of the pci data bus driven during the data phase. p_par 1i/o sync(p) rst(p) pci bus parity is even parity across p_ad[31:0] and p_c/be[3:0]# . p_par64 1i/o sync(p) rst(p) pci bus upper dword parity is even parity across p_ad[63:32] and p_c/be[7:4]# . p_c/be[3:0]# 4i/o sync(p) rst(p) pci bus command and byte enables are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables for p_ad[31:0] . p_c/be[7:4]# 4i/o sync(p) rst(p) pci bus byte enables are as byte enables for p_ad[63:32] during the data phase. p_req# 1o rst(p) pci bus request indicates to the pci bus arbiter that the 80321 desires use of the pci bus. p_req64# 1i/o sync(p) rst(p) pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of p_ack64# . p_gnt# 1i sync(p) pci bus grant indicates that access to the pci bus has been granted. p_ack64# 1i/o sync(p) rst(p) pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its address as the target of the current access and the target transfers data using the full 64-bit data bus. p_frame# 1i/o sync(p) rst(p) pci bus cycle frame is asserted to indicate the beginning and duration of an access. p_irdy# 1i/o sync(p) rst(p) pci bus initiator ready indicates the initiating agent ? s ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the address/data bus. during a read, it indicates the processor is ready to accept the data. p_trdy# 1i/o sync(p) rst(p) pci bus target ready indicates the target agent ? s ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the address/data bus. during a write, it indicates the target is ready to accept the data. p_stop# 1i/o sync(p) rst(p) pci bus stop indicates a request to stop the current transaction on the pci bus. p_devsel# 1i/o sync(p) rst(p) pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. p_serr# 1i/o od sync(p) rst(p) pci bus system error is driven for address parity errors on the pci bus. p_clk 1i pci bus input clock provides the timing for all pci transactions and is the clock source for most internal 80321 units. intel ? 80321 i/o processor package information 20 february 2003 datasheet p_rst# 1i async reset brings pci-specific registers, sequencers, and signals to a consistent state. when p_rst# is asserted: pci output signals are driven to a known consistent state. pci bus interface output signals are three-stated. open drain signals such as p_serr# are floated. p_rst# may be asynchronous to p_clk when asserted or deasserted. although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. p_perr# 1 i/o sync(p) rst(p) pci bus parity error is asserted when a data parity error occurs during a pci bus transaction. p_idsel 1i sync(p) pci bus initialization device select is used to select the 80321 during a configuration read or write command on the pci bus. p_int[a:d]# 4o od async rst(p) pci bus interrupt requests an interrupt. the assertion and deassertion of p_int[a:d]# is asynchronous to p_clk . a device asserts its p_int[a:d]# line when requesting attention from its device driver. once the p_int[a:d]# signal is asserted, it remains asserted until the device driver clears the pending request. p_int[a:d]# interrupts are level sensitive. p_m66en 1i pci bus 66 mhz enable indicates the speed of the pci bus. when this signal is sampled high the pci bus speed is 66 mhz, when low the bus speed is 33 mhz. table 6. serial port interface signals name count type description sscko 1o serial port clock out is the output bit-rate clock. sfrm 1o sync(ss) rst(m) serial frame indicates the beginning and end of a serial data word. txd 1o sync(ss) rst(m) transmit data is the outbound serial data pin. rxd 1i sync(ss) receive data is the inbound serial data pin. sscki 1i serial port clock in is the input bit-rate clock which may be used when a frequency other than the default of 3.7 mhz is needed. table 5. pci bus signals (sheet 2 of 2) name count type description intel ? 80321 i/o processor package information datasheet february 2003 21 table 7. miscellaneous signals (sheet 1 of 2) name count type description p_bmi 1o async rst(m) pci-x bus master indicator is an output used for hiding an i/o controller on the same bus segment as the 80321 by controlling the idsel line of that i/o controller. the output state of this signal is controlled by bit 0 of the gpod register and the default state at reset is 0. when not being used, this pin will be a nc. please see the 80321 specification update, specification clarification section for more details. xint[3:0]# 4i async external interrupt requests are used by external devices to request interrupt service. these pins are level-detect only and are internally synchronized. these interrupts may be directed to either the pci pins p_int[a:d]# or to the 80321 interrupt controller pins xint[3:0]# as shown below. xint[0]# ? p_int[a]# or xint[0]# xint[1]# ? p_int[b]# or xint[1]# xint[2]# ? p_int[c]# or xint[2]# xint[3]# ? p_int[d]# or xint[3]# hpi# 1i async high priority interrupt causes a high priority non-maskable interrupt to the 80321. this pin is level-detect only and is internally synchronized. gpio[3:0] 4i/o async rst(m) general purpose input/output . these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. gpio[4] / sda1 1i/o async rst(p) i/o od rst(m) general purpose input/output . these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. i 2 c data is used for data transfer and arbitration on the i 2 c bus. this is one of two i 2 c buses that the user may enable. 2.7k pull-up is required. gpio[5] / scl1 1i/o async rst(p) i/o od rst(m) general purpose input/output . these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. i 2 c clock provides synchronous operation of the i 2 c bus. this is one of two i 2 c buses that the user may enable. 2.7k pull-up is required. gpio[6] / sda0 1i/o async rst(p) i/o od rst(m) general purpose input/output . these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. i 2 c data is used for data transfer and arbitration on the i 2 c bus. this is one of two i 2 c buses that the user may enable. 2.7k pull-up is required. gpio[7] / scl0 1i/o async rst(p) i/o od rst(m) general purpose input/output . these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. i 2 c clock provides synchronous operation of the i 2 c bus. this is one of two i 2 c buses that the user may enable. 2.7k pull-up is required. tck 1i rst(t) test clock is an input which provides the clocking function for the ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge. tdi 1i sync(t) rst(t) test data input is the serial input pin for the jtag feature. tdi is sampled on the rising edge of tck , during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. tdo 1o sync(t)r st(t) test data output is the serial output pin for the jtag feature. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. the behavior of tdo is independent of p_rst# . intel ? 80321 i/o processor package information 22 february 2003 datasheet trst# 1i asyn rst(t) test reset asynchronously resets the test access port (tap) controller function of ieee 1149.1 boundary scan testing (jtag). this signal has a weak internal pull-up. tms 1i sync(t) rst(t) test mode select is sampled at the rising edge of tck to select the operation of the test logic for ieee 1149.1 boundary scan testing. this signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. rcomp 1i resister compensation is connected through a 30.1 ? 1% 1/4 w resister to ground. this is used to minimize the pci pin variations due to voltage and temperature variations. pwrdelay 1i async power fail delay is used with external delay circuits to delay the reset of the memory controller in a power-fail condition. this allows the self-refresh command to be sent to the ddr sdram array. por# 1i power on reset should be tied to the 1.3 v supply. it is used to provide clocks to the core from an internal ring oscillator during power up, which prevents internal contention. it also tristates the other pins to prevent external power sequencing contention. nc[2:0] 3i/o no connect pins have no usable function. however they are in the boundary scan chain and must not be connected to any signal, power or ground. v ccpll1 1pwr pll power is a separate v cc13 supply ball for the phase lock loop clock generator. it is to be connected to the board v cc13 plane. in noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. v ccpll2 1pwr pll power is a separate v cc13 supply ball for the phase lock loop clock generator. it is to be connected to the board v cc13 plane. in noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. v cc33 51 pwr 3.3 v power balls to be connected to a 3.3 v power board plane. v cc25 38 pwr 2.5 v power balls to be connected to a 2.5 v power board plane. v cc13 34 pwr 1.3 v power balls to be connected to a 1.3 v power board plane. v ss 118 gnd ground balls to be connected to a ground board plane. table 7. miscellaneous signals (sheet 2 of 2) name count type description intel ? 80321 i/o processor package information datasheet february 2003 23 table 8. pin mode behavior (sheet 1 of 2) pin reset norm hold 32-bit pci 32-bit mem ecc off rcveni# vivi---- rcveno# 1*vo---- m_ck[2:0] vo vo - - - - m_ck[2:0]# vo vo - - - - m_rst# 0vo - - - - sa[12:0] 0*vo---- sba[1:0] 0*vo---- sras# 1*vo---- scas# 1*vo---- swe# 1*vo---- sce[1:0]# 1*vo---- scke[1:0] 0*vo---- dq[63:32] z* vb - - id - q[31:0] z*vb---- scb[7:0] z* vb - - - id dqs[7:4] z* vb - - id - dqs[3:0] z*vb---- dqs[8] z* vb - - - id sdqm[7:4] z* vo - - z - sdqm[3:0] z*vo---- sdqm[8] z* vo - - - z ad[31:16] 0vbz - - - ad[15:8] 0vbz - - - ad[7:0] 0vbz - - - a[3:2] 0voz - - - be[3:0]# 1voz - - - ale 0voz - - - ads# 1voz - - - pb_clk vo vo - - - - w/r# 0voz - - - fwe# 1voz - - - den# 1voz - - - blast# 1voz - - - rdyrcv# vovi---- hold vivi---- holda vo vo 1 - - - pb_rst# 0vo - - - - pce[5]# / pbi100mhz# hvo1 - - - pce[4]# / pbi66mhz# hvo1 - - - pce[3]# / p_boot16# hvo1 - - - pce[2]# / 32bitpci# hvo1 - - - pce[1]# / retry hvo1 - - - pce[0]# / rst_mode# hvo1 - - - width[1:0] 0voz - - - intel ? 80321 i/o processor package information 24 february 2003 datasheet p_ad[63:32] zvb - h - - p_ad[31:16] zvb---- p_ad[15:0] zvb---- p_par zvb---- p_par64 zvb - h - - p_c/be[3:0]# zvb---- p_c/be[7:4]# zvb - h - - p_req# zvo---- p_req64# zvb---- p_gnt# vi vi - - - - p_ack64# zvb---- p_frame# vi vb - - - - p_irdy# vi vb - - - - p_trdy# vi vb - - - - p_stop# vi vb - - - - p_devsel# vi vb - - - - p_serr# zvb---- p_clk vi vi - - - - p_rst# vi vi - - - - p_perr# zvb---- p_idsel vi vi - - - - p_int[a:d]# zvo---- p_m66en vi vi - - - - sscko vo vo - - - - sfrm vo vo - - - - txd vo vo - - - - rxd vi vi - - - - sscki vi vi - - - - p_bmi 0vo---- xint[3:0]# vi vi - - - - hpi# vi vi - - - - gpio[7] vi vb - - - - gpio[6] vi vb - - - - gpio[5] vi vb - - - - gpio[4:0] vi vb - - - - tck vi vi - - - - tdi hh---- tdo zvo---- trst# hh---- tms hh---- pwrdelay vi vi - - - - nc[2:0] hh---- notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled h = pulled up to v cc pd = pull-up disabled notes: (continued) l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin. vo = a valid output level is driven. vi = need to drive a valid input level. * = after power fail sequence completes. ** = caused by hi-z from mode pins only. table 8. pin mode behavior (sheet 2 of 2) pin reset norm hold 32-bit pci 32-bit mem ecc off intel ? 80321 i/o processor package information datasheet february 2003 25 3.1.2 544-lead pbga package figure 2. 544-lead pbga package (top view) b1100-01 35.00 0.20 35.00 0.20 35.00 0.25 35.00 0.25 22.00 ref 22.00 ref top view side view pin 1 id 45 o chamfer (4 places) pin a1 corner 1.17 0.05 0.61 0.06 0.60 0.10 2.38 0.21 30 o seating plane -c- c -a- -b- 0.127 c 0.15 0.20 a 0.127 2 intel ? 80321 i/o processor package information 26 february 2003 datasheet figure 3. 544-lead pbga package (bottom view) a9257-01 1.63 ref 1.27 1.63 ref 1.27 0.90 0.60 ? 1.0 (3 places) pin #1corner a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ? b s a s c 1 ? 0.30 s intel ? 80321 i/o processor package information datasheet february 2003 27 figure 4. ball map - left side - top view b1102-01 a 12345 678910111213 12345 678910111213 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af dq35 dq38 scb3 scb1 scb2 scb5 dq30t dq28 dq29 scb0 sa2 sa3 sa4 dq34 dqs4 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc13 vcc13 vcc13 vcc13 vcc13 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc13 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 dqs6 dq53 dq52 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 sdqm 4 sdqm 8 rev veno# rev veni# dq33 dqs8 vref scb7 vss dq39 dq36 dq27 dq24 dq37 dq32 dq31 dq26 dq25 sa1 sa0 sa10 sras# dq45 sdqm5 dq46 dq47 dq43 dq42 dq60 dq51 sce1# sce0# dq62 dq58 sdqm7 dqs7 dqs5 dq41 scas# dq49 dq48 swe# sdqm6 dq50 dq54 dq55 dq59 m_ ck2# m_ ck1 m_ ck1# p_ intb# p_ inta# p_ intd# p_ ad31 p_ ad29 p_ ad27 p_ ad28 p_ ad25 p_ ad23 p_ ad19 p_ ad17 p_ cbe2# p_ irdy# p_ perr# p_ serr# p_ cbe1# p_ ad12 p_ ad10 p_ ad8 p_ ad5 p_ ad1 p_ cbe6# p_ ad63 p_ ad59 p_ dev sel# p_ ad14 p_ ad7 p_ ad61 p_ ack64# vcc pll2 vcc pll1 p_ ad13 p_ ad2 p_ ad0 p_ par64 p_ ad58 p_ ad60 p_ ad3 p_ m66en p_ cbe5# p_ ad6 p_ ad11 p_ ad15 p_ stop# p_ par p_ cbe0# p_ clk p_ cbe4# p_ trdy# p_ frame # p_ req64 # p_ ad21 p_ ad18 p_ ad16 p_ ad9 p_ ad4 p_ ad62 p_ cbe7# p_ cbe3# p_ idsel p_ ad22 p_ ad20 p_ ad24 p_ ad26 p_ gnt# p_ ad30 r_ req# r_ intc# r_ rst# m_ ck0# m_ ck0 m_ ck2 dq63 dq57 dq61 dq56 dq44 dq40 scb6 scb4 dqs3 sa5 sba0 sba1 sa6 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss rcomp vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss sdqm 3 vss vss vss vss vss vss vss vss intel ? 80321 i/o processor package information 28 february 2003 datasheet figure 5. ball map - right side - top view b1103-01 14 15 16 17 18 19 20 21 22 23 24 25 26 14 15 16 17 18 19 20 21 22 23 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af dq18 dq14 dqs2 dqs1 dqs8 dqs6 dq5 dq0 dqs0 dq20 sa8 sa7 dq21 dq2 dq4 dq13 scke0 scke1 sa9 dq23 dq17 dq19 sdqm2 dq22 dq10 dq3 dq16 dq11 dq15 dq9 dq7 m- rst# sdqm1 sdqm0 dq12 dq1 sa11 sa12 vcc25 vcc25 vcc25 vcc25 vcc23 vcc25 vcc25 vcc13 vcc13 vcc13 vcc13 vcc33 vcc13 vcc33 vcc13 vcc33 vcc33 vcc33 vcc33 vcc33 vcc13 vcc33 vcc33 vcc33 vcc33 vcc33 vcc13 vcc13 vcc13 vcc33 pce0# vcc13 vcc33 vcc13 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc33 vcc13 vcc13 vcc13 vcc13 vcc13 vcc13 vcc25 vcc25 vcc25 vcc25 vcc25 vcc25 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss hpi# tdo trst# xint 3# xint 2# xint 1# xint 0# tck tdi tms por# vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss ad31 ad30 ad28 ad26 ad27 ad25 ad23 ad20 ad24 ad22 ad18 ad19 ad17 be3# ad21 be2# be1# ad8 ad7 ad5 be0# ad15 ad16 ad14 ad9 ad10 ad8 ad3 a3 ad4 a2 ad0 ad2 ad1 pce5# pce4# pce3# pce2# gpio7 gpio6 gpio5 gpio3 gpio2 gpio1 gpio0 txd rxd sfrm sscki sscko gpio4 pce1# nc0 nc1 p_ bmi rdy rcv# p_ ad54 p_ ad56 p_ ad52 p_ ad50 p_ ad44 p_ ad42 p_ ad36 p_ ad34 p_ ad35 p_ ad38 p_ ad46 p_ ad49 p_ ad53 p_ ad45 p_ ad39 p_ ad33 p_ ad37 p_ ad41 p_ ad43 p_ ad47 p_ ad51 p_ ad55 pwr delay p_ ad57 p_ ad48 p_ ad40 p_ ad32 blast # den# w/r# fwe# ads# ale holda hold pb_ clk pb_ rst# ad12 ad13 ad11 width 1 width 0 ad29 vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss intel ? 80321 i/o processor package information datasheet february 2003 29 table 9. 544-lead pbga package - alphabetical ball listing (sheet 1 of 5) ball signal ball signal ball signal a1 sa1 b13 v ss c25 ad29 a2 dq35 b14 sa7 c26 ad28 a3 dq38 b15 v ss d1 sras# a4 dq34 b16 dq21 d2 sba0 a5 dq33 b17 v ss d3 sba1 a6 v ref b18 scke1 d4 v ss a7 scb3 b19 v ss d5 dq37 a8 sdqm8 b20 dq13 d6 dq32 a9 scb0 b21 v ss d7 rcveni# a10 sa2 b22 dq2 d8 scb2 a11 dq30 b23 v ss d9 scb5 a12 sdqm3 b24 dq4 d10 dq31 a13 dq28 b25 v ss d11 dq26 a14 sa8 b26 ad30 d12 dq25 a15 dq18 c1 sa10 d13 sa6 a16 dqs2 c2 v ss d14 dq19 a17 dq20 c3 v cc25 d15 sdqm2 a18 scke0 c4 sdqm4 d16 dq16 a19 dq14 c5 dq36 d17 sa11 a20 dqs1 c6 v cc25 d18 dq11 a21 dq8 c7 scb7 d19 dq15 a22 dq6 c8 scb1 d20 dq9 a23 dqs0 c9 v cc25 d21 m_rst# a24 dq5 c10 sa4 d22 dq7 a25 dq0 c11 dq27 d23 ad25 a26 ad31 c12 v cc25 d24 ad27 b1 sa0 c13 dq24 d25 v ss b2 dq39 c14 dq23 d26 ad26 b3 v ss c15 v cc25 e1 dq45 b4 dqs4 c16 dq17 e2 v ss b5 v ss c17 sa9 e3 dq44 b6 rcveno# c18 v cc25 e4 dq40 b7 v ss c19 sdqm1 e5 v cc25 b8 dqs8 c20 dq12 e6 v ss b9 v ss c21 v cc25 e7 scb6 b10 sa3 c22 sdqm0 e8 v ss b11 v ss c23 dq1 e9 scb4 b12 dq29 c24 v cc25 e10 v ss intel ? 80321 i/o processor package information 30 february 2003 datasheet e11 dqs3 f23 ad21 j1 dqs6 e12 v ss f24 v cc33 j2 v ss e13 sa5 f25 v ss j3 v cc25 e14 v ss f26 ad20 j4 dq53 e15 dq22 g1 dq46 j5 dq52 e16 v ss g2 v ss j6 v cc25 e17 sa12 g3 dq47 j7 v cc13 e18 v ss g4 dq43 j20 v cc13 e19 dq10 g5 dq42 j21 v cc33 e20 v ss g6 v cc25 j22 v ss e21 dq3 g7 v cc13 j23 ad11 e22 v ss g8 v cc13 j24 v cc33 e23 be3# g9 v cc13 j25 ad13 e24 ad22 g10 v cc13 j26 ad12 e25 ad24 g17 v cc13 k1 dq50 e26 ad23 g18 v cc13 k2 dq54 f1 sdqm5 g19 v cc13 k3 sdqm6 f2 dqs5 g20 v cc13 k4 dq55 f3 v cc25 g21 v cc33 k5 v ss f4 dq41 g22 v ss k6 v cc25 f5 v ss g23 be1# k7 v cc13 f6 v cc25 g24 ad17 k20 v cc13 f7 v cc25 g25 ad19 k21 v cc33 f8 v cc25 g26 ad18 k22 width0 f9 v cc25 h1 dq49 k23 ad8 f10 v cc25 h2 dq48 k24 ad10 f11 v cc25 h3 scas# k25 v ss f12 v cc25 h4 swe# k26 ad9 f13 v cc25 h5 v ss l1 dq60 f14 v cc25 h6 v cc25 l2 v ss f15 v cc25 h7 v cc13 l3 dq51 f16 v cc25 h20 v cc13 l4 sce1# f17 v cc25 h21 v cc33 l5 sce0# f18 v cc25 h22 width1 l6 v cc25 f19 v cc25 h23 ad14 l11 v ss f20 v cc25 h24 ad16 l12 v ss f21 v cc25 h25 v ss l13 v ss f22 be2# h26 ad15 l14 v ss table 9. 544-lead pbga package - alphabetical ball listing (sheet 2 of 5) ball signal ball signal ball signal intel ? 80321 i/o processor package information datasheet february 2003 31 l15 v ss n21 v cc33 r23 rdyrcv# l16 v ss n22 v ss r24 v cc33 l21 v cc33 n23 a2 r25 blast# l22 v ss n24 ad0 r26 den# l23 be0# n25 ad2 t1 m_ck1# l24 ad5 n26 ad1 t2 p_intb# l25 ad7 p1 dq59 t3 p_inta# l26 ad6 p2 m_ck2# t4 rcomp m1 dq57 p3 m_ck2 t5 v ss m2 dq61 p4 dq63 t6 v cc33 m3 v cc25 p5 v ss t11 v ss m4 dq56 p6 v cc25 t12 v ss m5 v ss p11 v ss t13 v ss m6 v cc25 p12 v ss t14 v ss m11 v ss p13 v ss t15 v ss m12 v ss p14 v ss t16 v ss m13 v ss p15 v ss t21 v cc13 m14 v ss p16 v ss t22 pb_rst# m15 v ss p21 v cc13 t23 holda m16 v ss p22 fwe# t24 hold m21 v cc13 p23 w/r# t25 v ss m22 a3 p24 ads# t26 pb_clk m23 ad4 p25 v ss u1 p_intd# m24 v cc33 p26 ale u2 v ss m25 v ss r1 m_ck1 u3 p_req# m26 ad3 r2 v ss u4 p_intc# n1 dq62 r3 v cc25 u5 p_rst# n2 v ss r4 m_ck0# u6 v cc33 n3 dq58 r5 m_ck0 u7 v cc13 n4 sdqm7 r6 v cc25 u20 v cc13 n5 dqs7 r11 v ss u21 v cc33 n6 v cc25 r12 v ss u22 v ss n11 v ss r13 v ss u23 pce5# n12 v ss r14 v ss u24 pce4# n13 v ss r15 v ss u25 pce3# n14 v ss r16 v ss u26 pce2# n15 v ss r21 v cc33 v1 p_ad31 n16 v ss r22 v ss v2 p_gnt# table 9. 544-lead pbga package - alphabetical ball listing (sheet 3 of 5) ball signal ball signal ball signal intel ? 80321 i/o processor package information 32 february 2003 datasheet v3 v cc33 y19 v cc13 ab5 v ss v4 p_ad30 y20 v cc13 ab6 p_ad9 v5 v ss y21 v cc33 ab7 v ss v6 v cc33 y22 gpio3 ab8 p_ad$ v7 v cc13 y23 gpio2 ab9 v ss v20 v cc13 y24 gpio1 ab10 p_cbe7# v21 v cc33 y25 v ss ab11 v ss v22 pce0# y26 gpio0 ab12 p_ad62 v23 nc0 aa1 p_ad23 ab13 v ss v24 v cc33 aa2 v ss ab14 p_ad54 v25 v ss aa3 v cc33 ab15 v ss v26 pce1# aa4 p_ad22 ab16 p_ad48 w1 p_ad29 aa5 p_ad20 ab17 v ss w2 v ss aa6 v cc33 ab18 p_ad40 w3 p_ad27 aa7 v cc33 ab19 v ss w4 p_ad28 aa8 v cc33 ab20 p_ad32 w5 p_ad26 aa9 v cc33 ab21 v ss w6 v cc33 aa10 v cc33 ab22 v cc33 w7 v cc13 aa11 v cc33 ab23 hpi# w20 v cc13 aa12 v cc13 ab24 sscki w21 v cc33 aa13 v cc33 ab25 v ss w22 v ss aa14 v cc13 ab26 sscko w23 gpio7 aa15 v cc33 ac1 p_ad17 w24 gpio6 aa16 v cc13 ac2 v ss w25 gpio5 aa17 v cc33 ac3 p_frame# w26 gpio4 aa18 v cc33 ac4 p_trdy# y1 p_ad25 aa19 v cc33 ac5 p_ad13 y2 p_cbe3# aa20 v cc33 ac6 p_cbe0# y3 p_ad24 aa21 v cc33 ac7 p_clk y4 p_idsel aa22 v ss ac8 p_ad2 y5 v ss aa23 sfrm ac9 p_ad0 y6 v cc33 aa24 v cc33 ac10 p_req64# y7 v cc13 aa25 rxd ac11 p_par64 y8 v cc13 aa26 txd ac12 p_cbe4# y9 v cc13 ab1 p_ad19 ac13 p_ad58 y10 v cc13 ab2 p_ad21 ac14 p_ad56 y17 v cc13 ab3 p_ad18 ac15 p_ad52 y18 v cc13 ab4 p_ad16 ac16 p_ad50 table 9. 544-lead pbga package - alphabetical ball listing (sheet 4 of 5) ball signal ball signal ball signal intel ? 80321 i/o processor package information datasheet february 2003 33 ac17 p_ad44 ad21 v cc33 ae24 v ss ac18 p_ad42 ad22 tck ae25 v cc33 ac19 p_ad36 ad23 nc1 ae26 v cc33 ac20 p_ad34 ad24 v cc33 af1 p_devsel# ac21 tdo ad25 v ss af2 p_perr# ac22 trst# ad26 xint0# af3 p_serr# ac23 v ss ae1 p_irdy# af4 p_cbe1# ac24 xint3# ae2 v ss af5 v ccpll1 ac25 xint2# ae3 p_par af6 p_ad12 ac26 xint1# ae4 v ss af7 p_ad10 ad1 p_cbe2# ae5 p_ad14 af8 p_ad8 ad2 p_stop# ae6 v ss af9 p_ad5 ad3 v cc33 ae7 v ccpll2 af10 p_ad1 ad4 p_ad15 ae8 v ss af11 p_cbe6# ad5 p_ad11 ae9 p_ad7 af12 p_ad63 ad6 v cc33 ae10 v ss af13 p_ad59 ad7 p_ad6 ae11 p_ack64# af14 p_ad55 ad8 p_m66en ae12 v ss af15 p_ad51 ad9 v cc33 ae13 p_ad61 af16 p_ad47 ad10 p_ad3 ae14 v ss af17 p_ad43 ad11 p_cbe5# ae15 p_ad53 af18 p_ad41 ad12 v cc33 ae16 v ss af19 p_ad37 ad13 p_ad60 ae17 p_ad45 af20 p_ad33 ad14 p_ad57 ae18 v ss af21 por# ad15 v cc33 ae19 p_ad39 af22 tms ad16 p_ad49 ae20 v ss af23 pwrdelay ad17 p_ad46 ae21 tdi af24 v cc33 ad18 v cc33 ae22 v ss af25 v cc33 ad19 p_ad38 ae23 p_bmi af26 v cc33 ad20 p_ad35 table 9. 544-lead pbga package - alphabetical ball listing (sheet 5 of 5) ball signal ball signal ball signal intel ? 80321 i/o processor package information 34 february 2003 datasheet table 10. 544-lead pbga package - alphabetical signal listing (sheet 1 of 5) signal ball signal ball signal ball a2 n23 be2# f22 dq34 a4 a3 m22 be3# e23 dq35 a2 ad0 n24 blast# r25 dq36 c5 ad1 n26 den# r26 dq37 d5 ad2 n25 dq0 a25 dq38 a3 ad3 m26 dq1 c23 dq39 b2 ad4 m23 dq2 b22 dq40 e4 ad5 l24 dq3 e21 dq41 f4 ad6 l26 dq4 b24 dq42 g5 ad7 l25 dq5 a24 dq43 g4 ad8 k23 dq6 a22 dq44 e3 ad9 k26 dq7 d22 dq45 e1 ad10 k24 dq8 a21 dq46 g1 ad11 j23 dq9 d20 dq47 g3 ad12 j26 dq10 e19 dq48 h2 ad13 j25 dq11 d18 dq49 h1 ad14 h23 dq12 c20 dq50 k1 ad15 h26 dq13 b20 dq51 l3 ad16 h24 dq14 a19 dq52 j5 ad17 g24 dq15 d19 dq53 j4 ad18 g26 dq16 d16 dq54 k2 ad19 g25 dq17 c16 dq55 k4 ad20 f26 dq18 a15 dq56 m4 ad21 f23 dq19 d14 dq57 m1 ad22 e24 dq20 a17 dq58 n3 ad23 e26 dq21 b16 dq59 p1 ad24 e25 dq22 e15 dq60 l1 ad25 d23 dq23 c14 dq61 m2 ad26 d26 dq24 c13 dq62 n1 ad27 d24 dq25 d12 dq63 p4 ad28 c26 dq26 d11 dqs0 a23 ad29 c25 dq27 c11 dqs1 a20 ad30 b26 dq28 a13 dqs2 a16 ad31 a26 dq29 b12 dqs3 e11 ads# p24 dq30 a11 dqs4 b4 ale p26 dq31 d10 dqs5 f2 be0# l23 dq32 d6 dqs6 j1 be1# g23 dq33 a5 dqs7 n5 intel ? 80321 i/o processor package information datasheet february 2003 35 dqs8 b8 p_ad14 ae5 p_ad52 ac15 fwe# p22 p_ad15 ad4 p_ad53 ae15 gpio0 y26 p_ad16 ab4 p_ad54 ab14 gpio1 y24 p_ad17 ac1 p_ad55 af14 gpio2 y23 p_ad18 ab3 p_ad56 ac14 gpio3 y22 p_ad19 ab1 p_ad57 ad14 gpio4 w26 p_ad20 aa5 p_ad58 ac13 gpio5 w25 p_ad21 ab2 p_ad59 af13 gpio6 w24 p_ad22 aa4 p_ad60 ad13 gpio7 w23 p_ad23 aa1 p_ad61 ae13 hold t24 p_ad24 y3 p_ad62 ab12 holda t23 p_ad25 y1 p_ad63 af12 hpi# ab23 p_ad26 w5 p_cbe0# ac6 m_ck0 r5 p_ad27 w3 p_cbe1# af4 m_ck0# r4 p_ad28 w4 p_cbe2# ad1 m_ck1 r1 p_ad29 w1 p_cbe3# y2 m_ck1# t1 p_ad30 v4 p_cbe4# ac12 m_ck2 p3 p_ad31 v1 p_cbe5# ad11 m_ck2# p2 p_ad32 ab20 p_cbe6# af11 m_rst# d21 p_ad33 af20 p_cbe7# ab10 nc0 v23 p_ad34 ac20 p_clk ac7 nc1 ad23 p_ad35 ad20 p_devsel# af1 p_bmi ae23 p_ad36 ac19 p_frame# ac3 p_ack64# ae11 p_ad37 af19 p_gnt# v2 p_ad0 ac9 p_ad38 ad19 p_idsel y4 p_ad1 af10 p_ad39 ae19 p_inta# t3 p_ad2 ac8 p_ad40 ab18 p_intb# t2 p_ad3 ad10 p_ad41 af18 p_intc# u4 p_ad4 ab8 p_ad42 ac18 p_intd# u1 p_ad5 af9 p_ad43 af17 p_irdy# ae1 p_ad6 ad7 p_ad44 ac17 p_m66en ad8 p_ad7 ae9 p_ad45 ae17 p_par ae3 p_ad8 af8 p_ad46 ad17 p_par64 ac11 p_ad9 ab6 p_ad47 af16 p_perr# af2 p_ad10 af7 p_ad48 ab16 p_req# u3 p_ad11 ad5 p_ad49 ad16 p_req64# ac10 p_ad12 af6 p_ad50 ac16 p_rst# u5 p_ad13 ac5 p_ad51 af15 p_serr# af3 table 10. 544-lead pbga package - alphabetical signal listing (sheet 2 of 5) signal ball signal ball signal ball intel ? 80321 i/o processor package information 36 february 2003 datasheet p_stop# ad2 scb4 e9 v cc13 j20 p_trdy# ac4 scb5 d9 v cc13 k7 pb_clk t26 scb6 e7 v cc13 k20 pb_rst# t22 scb7 c7 v cc13 u7 pce0# v22 scke0 a18 v cc13 u20 pce1# v26 scke1 b18 v cc13 v7 pce2# u26 sce0# l5 v cc13 w7 pce3# u25 sce1# l4 v cc13 w20 pce4# u24 sdqm0 c22 v cc13 y7 pce5# u23 sdqm1 c19 v cc13 y8 por# af21 sdqm2 d15 v cc13 y9 pwrdelay af23 sdqm3 a12 v cc13 y10 sras# d1 sdqm4 c4 v cc13 y17 rcomp t4 sdqm5 f1 v cc13 y19 rcveni# d7 sdqm6 k3 v cc13 y20 rcveno# b6 sdqm7 n4 v cc13 m21 rdyrcv# r23 sdqm8 a8 v cc13 p21 rxd aa25 sfrm aa23 v cc13 t21 sa0 b1 sscki ab24 v cc13 v20 sa1 a1 sscko ab26 v cc13 y18 sa2 a10 tck ad22 v cc13 aa12 sa3 b10 tdi ae21 v cc13 aa14 sa4 c10 tdo ac21 v cc13 aa16 sa5 e13 tms af22 v cc25 c3 sa6 d13 trst# ac22 v cc25 c6 sa7 b14 txd aa26 v cc25 c9 sa8 a14 v cc25 f20 v cc25 c12 sa9 c17 v cc13 g7 v cc25 c15 sa10 c1 v cc13 g8 v cc25 c18 sa11 d17 v cc13 g9 v cc25 c21 sa12 e17 v cc13 g10 v cc25 c24 sba0 d2 v cc13 g17 v cc25 e5 sba1 d3 v cc13 g18 v cc25 f3 scas# h3 v cc13 g19 v cc25 f6 scb0 a9 v cc13 g20 v cc25 f7 scb1 c8 v cc13 h7 v cc25 f8 scb2 d8 v cc13 h20 v cc25 f9 scb3 a7 v cc13 j7 v cc25 f10 table 10. 544-lead pbga package - alphabetical signal listing (sheet 3 of 5) signal ball signal ball signal ball intel ? 80321 i/o processor package information datasheet february 2003 37 v cc25 f11 v cc33 aa21 v ss b3 v cc25 f12 v cc33 aa24 v ss b5 v cc25 f13 v cc33 ab22 v ss b7 v cc25 f14 v cc33 ad24 v ss b9 v cc25 f15 v cc33 aa3 v ss b11 v cc25 f16 v cc33 aa6 v ss b13 v cc25 f17 v cc33 aa7 v ss b15 v cc25 f18 v cc33 aa8 v ss b17 v cc25 f19 v cc33 aa9 v ss b19 v cc25 f21 v cc33 aa10 v ss b21 v cc25 g6 v cc33 aa11 v ss b23 v cc25 h6 v cc33 aa13 v ss b25 v cc25 j3 v cc33 aa15 v ss c2 v cc25 j6 v cc33 aa17 v ss d25 v cc25 k6 v cc33 aa18 v ss d4 v cc25 l6 v cc33 aa19 v ss e2 v cc25 m3 v cc33 aa20 v ss e6 v cc25 m6 v cc33 ad3 v ss e8 v cc25 n6 v cc33 ad6 v ss e10 v cc25 p6 v cc33 ad9 v ss e12 v cc25 r3 v cc33 ad12 v ss e14 v cc25 r6 v cc33 ad15 v ss e16 v cc33 f24 v cc33 ad18 v ss e18 v cc33 g21 v cc33 ad21 v ss e20 v cc33 h21 v cc33 ae25 v ss e22 v cc33 j21 v cc33 ae26 v ss f5 v cc33 j24 v cc33 af24 v ss f25 v cc33 k21 v cc33 af25 v ss g2 v cc33 l21 v cc33 af26 v ss g22 v cc33 m24 v cc33 t6 v ss h5 v cc33 n21 v cc33 u6 v ss h25 v cc33 r21 v cc33 v3 v ss j2 v cc33 r24 v cc33 v6 v ss j22 v cc33 u21 v cc33 w6 v ss k5 v cc33 v21 v cc33 y6 v ss k25 v cc33 v24 v ccpll1 af5 v ss l2 v cc33 w21 v ccpll2 ae7 v ss l11 v cc33 y21 v ref a6 v ss l12 table 10. 544-lead pbga package - alphabetical signal listing (sheet 4 of 5) signal ball signal ball signal ball intel ? 80321 i/o processor package information 38 february 2003 datasheet v ss l13 v ss r11 v ss ab15 v ss l14 v ss r12 v ss ab17 v ss l15 v ss r13 v ss ab19 v ss l16 v ss r14 v ss ab21 v ss l22 v ss r15 v ss ab25 v ss m5 v ss r16 v ss ac2 v ss m11 v ss r22 v ss ac23 v ss m12 v ss t5 v ss ad25 v ss m13 v ss t11 v ss ae2 v ss m14 v ss t12 v ss ae4 v ss m15 v ss t13 v ss ae6 v ss m16 v ss t14 v ss ae8 v ss m25 v ss t15 v ss ae10 v ss n2 v ss t16 v ss ae12 v ss n11 v ss t25 v ss ae14 v ss n12 v ss u2 v ss ae16 v ss n13 v ss u22 v ss ae18 v ss n14 v ss v5 v ss ae20 v ss n15 v ss v25 v ss ae22 v ss n16 v ss w2 v ss ae24 v ss n22 v ss w22 swe# h4 v ss p5 v ss y5 width00 k22 v ss p11 v ss y25 width01 h22 v ss p12 v ss aa2 w/r# p23 v ss p13 v ss aa22 xint0# ad26 v ss p14 v ss ab5 xint1# ac26 v ss p15 v ss ab7 xint2# ac25 v ss p16 v ss ab9 xint3# ac24 v ss p25 v ss ab11 v ss r2 v ss ab13 table 10. 544-lead pbga package - alphabetical signal listing (sheet 5 of 5) signal ball signal ball signal ball intel ? 80321 i/o processor package information datasheet february 2003 39 3.2 package thermal specifications the device is specified for operation when t c (case temperature) is within the range of 0 c to 105 c, depending on operating conditions. refer to the ?thermal data for the 544-lead pbga package? application note for more information regarding maximum case temperatures on the 544-lead pbga package. case temperature may be measured in any environment to determine whether the processor is within specified operating range. measure the case temperature at the center of the top surface, opposite the ballpad. 3.2.1 thermal specifications this section defines the terms used for thermal analysis. 3.2.1.1 ambient temperature ambient temperature, t a , is the temperature of the ambient air surrounding the package. in a system environment, ambient temperature is the temperature of the air upstream from the package. 3.2.1.2 case temperature when measuring case temperature, attention to detail is required to ensure accuracy. when a thermocouple is used, calibrate it before taking measurements. errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. to minimize measurement errors: use a 35 gauge k-type thermocouple or equivalent. attach the thermocouple bead or junction to the package top surface at a location corresponding to the center of the die ( figure 6 ). the center of the die gives a more accurate measurement and less variation as the boundary condition changes. attach the thermocouple bead at a 0 angle with respect to the package as shown in figure 6 , when no heatsink is attached. 3.2.1.3 thermal resistance the thermal resistance value for the case-to-ambient, figure 6. thermocouple attachment - no heatsink intel ? 80321 thermocouple i/o processor intel ? 80321 i/o processor package information 40 february 2003 datasheet 3.2.2 thermal analysis table 11 lists the case-to-ambient thermal resistances of the 80321 for different air flow rates with and without a heat sink. to calculate t a , the maximum ambient temperature to conform to a particular case temperature: t a = t c - p ( table 11. 544-lead pbga package thermal characteristics thermal resistance ? c/watt parameter airflow ? ft/min (m/sec) 0 (0) 50 (0.25) 100 (0.50) 200 (1.01) 300 (1.52) 400 (2.03) 600 (3.04) 800 (4.06) jc (junction-to-case) 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00 ca (case-to-ambient) without heatsink 15.87 14.72 13.99 12.94 12.20 11.73 10.90 10.39 notes: 1. this table applies to a h-pbga device soldered directly onto a board. 2. estimated value. ja jc ca intel ? 80321 i/o processor package information datasheet february 2003 41 3.3 socket information table 12 and table 13 provide vendor details for socket-headers and burn-in sockets for the 80321. this is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. 3.3.1 socket-header vendor 3.3.2 burn-in socket vendor 3.3.3 shipping tray vendor 3.3.4 logic analyzer interposer vendor table 12. socket-header vendor company factory representative phone/fax # part # bga 544-pin header bga 544-pin socket carrier adapter technologies 214-218 south 4th street perkasie, pa 18944 john miller 215 258-5750 215 258-5760 tbd tbd table 13. burn-in socket vendor company factory representative phone # burn-in socket part # ya m ai ch i 2235 zanker road san jose, ca 95131 steve drake tbd np276-67613. ac-14847 table 14. shipping tray vendor company factory representative phone # shipping tray part # daewon semiconductor sunna chung 82.31.794.2001 127-3535-919, rev. d table 15. logic analyzer interposer vendor company factory representative phone/fax # part # delphi connection systems 17150 von karmann avenue irvine, ca 92614-0968 bob betz 949 660-6968 949 660-5825 tbd intel ? 80321 i/o processor package information 42 february 2003 datasheet 3.3.5 jtag emulator vendor table 16. jtag emulator vendor company part # arm, ltd. www.arm.com multi-ice interface unit arm kp1-0019a windriver hsi www.windriver.com visionprobe/visionice for intel ? xscale ? microarchitecture intel ? 80321 i/o processor electrical specifications datasheet february 2003 43 4.0 electrical specifications 4.1 absolute maximum ratings 4.2 v ccpll pin requirements to reduce clock skew, the v ccpll1 , v ccpll2 , v sspll1 and v sspll2 balls for the phase lock loop (pll) circuit are isolated on the package. the lowpass filter, as shown in figure 7 , reduces noise induced clock jitter and its effects on timing relationships in system designs. the 4.7 f capacitor must be (low esr solid tantalum), the 0.01 f capacitor must be of the type x7r and the node connecting v ccpll must be as short as possible. the vsspll balls should be connected to the board ground plane. parameter maximum rating notice : the specifications are subject to change without notice. contact your local intel representative before finalizing a design. storage temperature ? 55 c to +125 c case temperature under bias 0 c to +105 c supply voltage v cc33 wrt. v ss ? 0.5 v to +4.1 v supply voltage v cc25 wrt. v ss ? 0.5 v to +3.6 v supply voltage v cc13 wrt. v ss ? 0.5 v to +2.1 vv voltage on any ball wrt. v ss ? 0.5 v to v ccp + 0.5 v ? war ning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 17. operating conditions symbol parameter min max units notes v cc33 3.3 v pci supply voltage 3.0 3.6 v v cc25 2.5 v ddr supply voltage 2.3 2.7 v v cc13 1.3 v core supply voltage 1.235 1.365 v v ccpll1 pll supply voltage v cc13 v cc13 v v ccpll2 pll supply voltage v cc13 v cc13 v v ref memory i/o reference voltage v cc25 /2 - 0.05 v cc25 /2 + 0.05 v f p_clk input clock frequency 16 133 mhz t c case temperature under bias 0 105 c figure 7. v ccpll lowpass filter 10 ? , 5%, 1/8w v cc13 (board plane) v ccpll 0.01f 4.7f + intel ? 80321 i/o processor electrical specifications 44 february 2003 datasheet 4.3 targeted dc specifications table 18. dc characteristics symbol parameter min max units notes v il1 input low voltage (sdram) -0.3 v ref - 0.15 v 3 , 5 v ih1 input high voltage (sdram) v ref + 0.15 v cc25 + 0.3 v 3 , 5 v il2 input low voltage (misc.) -0.3 0.8 v 4 v ih2 input high voltage (misc.) 2.0 v cc33 + 0.3 v 4 v il3 input low voltage (pci-x) -0.5 0.35 v cc33 v 1 v ih3 input high voltage (pci-x/pci) 0.5 v cc33 v cc33 + 0.5 v 1 v il4 input low voltage (pci) -0.5 0.3 v cc33 v 1 v ol1 output low voltage (misc.) 0.4 v i ol = 6 ma ( 4 ) v oh1 output high voltage (misc.) 2.4 v i oh = -2 ma ( 4 ) v ol2 output low voltage (sdram) 0.35 v i ol = 15.2 ma ( 3 , 5 ) v oh2 output high voltage (sdram) 1.95 v i oh = -15.2 ma ( 3 , 5 ) v ol3 output low voltage (pci-x) 0.1 v cc33 vi ol = 1500 a ( 1 ) v oh3 output high voltage (pci-x) 0.9 v cc33 vi oh = -500 a ( 1 ) c in input pin capacitance 8 pf 1 , 2 c clk clock pin capacitance 5 8 pf 1 , 2 l pin ball inductance 15 nh 1 , 2 notes: 1. as required by the pci-x addendum to the pci local bus specification, revision 1.0a. 2. not tested. 3. sdram signals include ma[12:0] , ba[1:0] , cas# , cs[1:0]# , cke[1:0] , dm[8:0] , ras# , we# , rcveni# , rcveno# , m_ck[2:0] , m_ck[2:0]# , dq[63:0] , dqs[8:0] and cb[7:0] . 4. miscellaneous signals include all signals that are not pci or sdram signals. 5. only 2.5 v ddr sdram is supported. intel ? 80321 i/o processor electrical specifications datasheet february 2003 45 ta ble 1 9. i cc characteristics symbol parameter typ max units notes i li1 input leakage current for each signal except tck , tms , trst# , tdi . 2 a0 intel ? 80321 i/o processor electrical specifications datasheet february 2003 47 4.4.2 pci interface signal timings table 21. pci signal timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes minmaxminmaxminmaxminmax t ov1 clock to output valid delay for bused signals 0.73.80.73.8 1 6 2 11 ns 1 , 2 , 3 t ov2 clock to output valid delay for point to point signals 0.73.80.73.8 2 6 2 12 ns 1 , 2 , 3 t of clock to output float delay 7 7 14 28 ns 1 , 7 t is1 input setup to clock for bused signals 1.2 1.7 3 7 ns 3 , 4 , 8 t is2 input setup to clock for point to point signals 1.2 1.7 5 10, 12 ns 3 , 4 t ih1 input hold time from clock 0.5 0.5 0 0 ns 4 t rst reset active time 1 1 1 1 ms t rf reset active to output float delay 40 40 40 40 ns 5 , 6 t is3 req64# to reset setup time 10 10 10 10 clocks t ih2 reset to req64# hold time 0 50 0 50 0 50 0 50 ns t is4 pci-x initialization pattern to reset setup time 10 10 clocks t ih3 reset to pci-x initialization pattern hold time 050050 ns notes: 1. see the timing measurement conditions in figure 9 ? output timing measurement waveforms ? on page 51 . 2. see figure 15 ? pci/pci-x tov(max) rising edge ac test load ? on page 55 , figure 16 ? pci/pci-x tov(max) falling edge ac test load ? on page 55 and figure 17 ? pci/pci-x tov(min) ac test load ? on page 56 . 3. setup time for point-to-point signals applies to req# and gnt# only. all other signals are bused. 4. see the timing measurement conditions in figure 10 ? input timing measurement waveforms ? on page 52 . 5. rst# is asserted and deasserted asynchronously with respect to clk. 6. all output drivers must be floated when rst# is active. 7. for purposes of active/float timing measurements, the hi-z or ? off ? state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. intel ? 80321 i/o processor electrical specifications 48 february 2003 datasheet 4.4.3 ddr sdram interface signal timings 4.4.4 peripheral bus interface signal timings table 22. ddr sdram signal timings symbol parameter min max units notes t vb1 dq, cb and dm output valid time before associated dqs 1.3 ns 4 t va1 dq, cb and dm output valid time after associated dqs 1.3 ns 4 t vb2 dqs output valid time before m_ck 1.4 ns 4 t va2 dqs output valid time after m_ck 1.0 ns 4 t vb3 address and control write output valid before m_ck 4.2 ns 4 t va3 address and control write output valid after m_ck 3.3 ns 4 t vb4 dqs read input valid time before dq 1.6 ns 5 t va4 dqs read input valid time after dq 1.6 ns 5 t vb5 rcveno# output valid time before m_ck 1.4 ns 5 t va5 rcveno# output valid time after m_ck 1.0 ns 5 t vb6 rcveni# input valid time before dqs 3.0 ns 5 t va6 rcveni# hold from dqs valid 0.8 ns 5 notes: 1. see figure 9 ? output timing measurement waveforms ? on page 51 . 2. see figure 10 ? input timing measurement waveforms ? on page 52 . 3. these output valid times are specified with a 0 pf loading. 4. see figure 12 ? ddr sdram write timings ? on page 53 . 5. see figure 13 ? ddr sdram read timings ? on page 54 . table 23. peripheral bus signal timings sym parameter min max units notes t ov1 output valid delay from pb_clk 15.5ns 1 , 3 t of output float delay from pb_clk 15.5ns 1 , 3 t is1 input setup to pb_clk 4.9 ns 2 t ih1 input hold from pb_clk 2ns 2 notes: 1. see figure 9 ? output timing measurement waveforms ? on page 51 . 2. see figure 10 ? input timing measurement waveforms ? on page 52 . 3. see figure 14 ? ac test load for all signals except pci and ddr sdram ? on page 55 . intel ? 80321 i/o processor electrical specifications datasheet february 2003 49 4.4.5 i 2 c interface signal timings 4.4.6 ssp interface signal timings ta ble 2 4. i 2 c signal timings symbol parameter std. mode fast mode units notes min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s 1 t hdsta hold time (repeated) start condition 4 0.6 s 1 , 3 t low scl clock low time 4.7 1.3 s 1 , 2 t high scl clock high time 4 0.6 s 1 , 2 t susta setup time for a repeated start condition 4.7 0.6 s 1 t hddat data hold time 0 3.45 0 0.9 s 1 t sudat data setup time 250 100 ns 1 t sr scl and sda rise time 1000 20+0.1c b 300 ns 1 , 4 t sf scl and sda fall time 300 20+0.1c b 300 ns 1 , 4 t susto setup time for stop condition 4 0.6 s 1 notes: 1. see figure 11 ? i 2 c interface signal timings ? on page 52 . 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf. table 25. ssp signal timings symbol parameter min max units notes t is input setup to sscko 9ns t ih input hold from sscko 0ns t ov output valid delay from sscko -1 2 ns t ov output valid delay from sscki to sscko in external clock mode. 310ns intel ? 80321 i/o processor electrical specifications 50 february 2003 datasheet 4.4.7 boundary scan test signal timings table 26. boundary scan test signal timings symbol parameter min max units notes t bsf tck frequency 0 66 mhz t bsch tck high time 7.5 ns measured at 1.5 v ( 1 ) t bscl tck low time 7.5 ns measured at 1.5 v ( 1 ) t bscr tck rise time 5 ns 0.8 v to 2.0 v ( 1 ) t bscf tck fall time 5 ns 2.0 v to 0.8 v ( 1 ) t bsis1 input setup to tck 3ns 4 t bsih1 input hold from tck 3ns 4 t bsov1 tdo output valid delay from falling edge of tck. 111ns 2 , 3 t of1 tdo output float delay from falling edge of tck. 111ns 2 , 5 notes: 1. not tested. 2. outputs precharged to v cc5 . 3. see figure 9 ? output timing measurement waveforms ? on page 51 . 4. see figure 10 ? input timing measurement waveforms ? on page 52 . 5. a float condition occurs when the output current becomes less than ilo. float delay is not tested. see figure 9 ? output timing measurement waveforms ? on page 51 . intel ? 80321 i/o processor electrical specifications datasheet february 2003 51 4.5 ac timing waveforms figure 8. clock timing measurement waveforms figure 9. output timing measurement waveforms t cf t cr t ch t cl t c v tch v ih(min) vil(max) v test v tcl v test clk output float vtrise output delay rise output delay fall v tfall t ov t ov t of v tl v th intel ? 80321 i/o processor electrical specifications 52 february 2003 datasheet figure 10. input timing measurement waveforms figure 11. i 2 c interface signal timings clk input valid v test v test v test t is t ih v tl v th v th v tl v max sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start intel ? 80321 i/o processor electrical specifications datasheet february 2003 53 figure 12. ddr sdram write timings m_ck dqs dq t va2 t vb2 t va1 t vb1 t vb3 t va3 addr/ctrl intel ? 80321 i/o processor electrical specifications 54 february 2003 datasheet figure 13. ddr sdram read timings dqs dq t vb4 t va 4 rcveno# rcveni# t vb6 t va5 t vb5 m_ck t va6 intel ? 80321 i/o processor electrical specifications datasheet february 2003 55 4.6 ac test conditions table 29. ac measurement conditions symbol pci-x pci ddr pbi units notes v tch 0.6 v cc33 0.6 v cc33 --v v tcl 0.2 v cc33 0.2 v cc33 --v v th 0.6 v cc33 0.6 v cc33 2.0 2.0 v v tl 0.25 v cc33 0.2 v cc33 0.5 0.8 v v test 0.4 v cc33 0.4 v cc33 1.25 1.5 v v trise 0.285 v cc33 0.285 v cc33 1.25 1.5 v v tfall 0.615 v cc33 0.615 v cc33 1.25 1.5 v v max 0.4 v cc33 0.4 v cc33 1.5 1.2 v slew rate 1.5 1.5 1.5 1.5 v/ns 1 1. input signal slew rate is measured between v il and v ih . figure 14. ac test load for all signals except pci and ddr sdram figure 15. pci/pci-x t ov(max) rising edge ac test load figure 16. pci/pci-x t ov(max) falling edge ac test load output 50pf tes t point output te st point 10pf 25 ? output 10pf 25 ? v cc33 tes t point intel ? 80321 i/o processor electrical specifications 56 february 2003 datasheet figure 17. pci/pci-x t ov(min) ac test load figure 18. pci_rst# vs. pwrdelay timings during power-up figure 19. pci_rst# vs. pwrdelay timings during power-down output te s t point 10pf 1k ? 1k ? v cc33 few m illiseconds pci_rst# pwrdelay brd_pwrdelay note: the delay depends on the size of the capacitor. a delay of about 1 ms is adequate. few milliseconds pci_rst# pwrdelay brd_pwrdelay note: the delay depends on the size of the capacitor. a delay of about 1 ms is adequate. |
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